The present embodiments relate to data storage circuits, and are more particularly directed to circuits such as registers and latches using a low threshold voltage output enable circuit.
In many modern circuit applications it is desirable to improve the speed of operation of the circuit application, and a common circuit application to which this desire applies is a register. A register is typically considered a device that is able to store information over time, where the storage time associated with the register is often one clock cycle. For further background FIG. 1 illustrates a schematic of a register designated generally at 10, where the following first discusses the components of register 10 followed by a description of its operation.
Register 10 includes an input 12 for receiving data D and an input 14 for receiving a clock signal CLK. Turning first to input 12, it is connected to a first output enable circuit 16, where circuit 16 is sometimes referred to in the art by other names such as a passgate or a transmission gate. In any event, output enable circuit 16 consists of a p-channel transistor 16p and an n-channel transistor 16n. A first source/drain of each transistor in circuit 16 is connected to input 12, and a second source/drain of each of those transistors is connected to a node 17 which is further connected to an input of an inverter 18. The output of inverter 18 is connected to the input of a feedback inverter 20, and the output of feedback inverter 20 is connected to the input of inverter 18. The output of inverter 18 is also connected to a node 19 which is connected to the input of a second output enable circuit 22. Second output enable circuit 22 consists of a p-channel transistor 22p and an n-channel transistor 22n. A first source/drain of each transistor in second output enable circuit 22 is connected to the output of inverter 18, and a second source/drain of each of those transistors is connected to a node 23 which is further connected to an input of an inverter 24. The output of inverter 24 is connected to the input of a feedback inverter 26, and the output of feedback inverter 26 is connected to the input of inverter 24. In addition, the output of inverter 24 provides the data output Q for register 10. Lastly, the clock signal CLK at input 14 is used to clock the transistors of output enable circuits 16 and 22. More particularly, input 14 is connected directly to the gates of p-channel transistor 16p and n-channel transistor 22n, and further to the input of an inverter 28. The inverted clock signal (shown in FIG. 1 as CLK) from the output of inverter 28 is connected to the gates of n-channel transistor 16n and p-channel transistor 22p.
The operation of register 10 is now described and is also illustrated with reference to the timing diagram of FIG. 2, where FIG. 2 across its top illustrates the clock signal CLK applied to register 10. Generally, CLK is periodic with a fifty percent duty cycle during typical active mode operations, and as seen below the CLK transitions thereby cause data to pass through register 10. However, by way of introduction to an important notion detailed later, note that the clock period is also shown for an extended time period between a time t.sub.8 and a time t.sub.9 to stay constant rather than cycling and, in the present example, to remain at a low level during this period. During this period, and as further appreciated below, register 10 remains inactive.
Turning now to the data transfer through register 10 during the active mode of operation, the following demonstrates the passage of data D from input 12 through the first stage of register 10, where that stage consists of output enable circuit 16 as well as the two-inverter combination following it. To further discuss this data transfer, attention is first directed to the second row in FIG. 2, which illustrates the data D coupled to input 12. For simplicity sake, prior to time t.sub.0 unknown data is shown as input although CLK is active prior to t.sub.0. At t.sub.0, a first data bit D1 is input to register 10. Further, at t.sub.0, note that CLK is low and is applied to the gate of p-channel transistor 16p, while its inverted form, CLK, is applied to the gate of n-channel transistor 16n. As a result, after some delay represented in FIG. 2 between t.sub.0 and t.sub.1, the low clock and its complement are enabling to one or both of transistors in output enable circuit 16, which thereby passes D1 from input 12 to node 17 as is shown by the third row in FIG. 2. Note that the term "enabling" is known in the art, and indicates that the gate potential is sufficient to cause conduction along the conductive path (i.e., the source/drain) of the transistor to which the gate potential is connected. Next, D1 at node 17 passes through and is inverted by inverter 18, which thereby adds a one inverter delay to the signal as it continues to pass through register 10 and appears as D1 at node 19, as shown at t.sub.2 in the fourth row in FIG. 2. At this point, therefore, one skilled in the art will appreciate that the data D1 is effectively latched at node 19, and its state is further retained by the feedback operation of inverter 20. In this regard, therefore, the combination of inverters 18 and 20 are referred to in this document as a data retention circuit.
Continuing with the data transfer through register 10, the following completes the passage of data D through the second stage of register 10, where that stage consists of output enable circuit 22 as well as the two-inverter combination following it. Once again looking to FIG. 2, at time t.sub.3 CLK rises to a high level, and this transition and new level is applied to the gate of n-channel transistor 22n, while its inverted form, CLK, is applied to the gate of p-channel transistor 22p. As a result, after some delay represented in FIG. 2 between t.sub.3 and t.sub.4, output enable circuit 22 operates via one or both of its transistors to pass D1 from node 19 to node 23 as is shown in the fifth row of FIG. 2. Next, D1 at node 23 passes through and is inverted by inverter 24, which thereby adds a one inverter delay to the signal and thereby concludes the path through register 10 since the data D then appears at output Q, as shown at t.sub.5 in the final row of FIG. 2. At this point, therefore, data D1 is latched at output Q with its state further maintained by the feedback operation of inverter 26, and that data may then be sampled by another circuit or the like requiring access to that data.
Having now demonstrated the passage of D1 through register 10 during its active mode of operation, the discussion of the operation of register 10 is now concluded with a more detailed examination of its inactive mode. Specifically, after CLK goes low starting at t.sub.6, and following the other transitions through register 10 as described above, then from t.sub.8 l to t.sub.9 there are no active transitions in register 10 since CLK remains low. During this time, therefore, the state of register 10 is unchanged. By way of introduction to an inventive aspect described later, however, it is noted that some of the transistors forming register 10 are conducting during this time, while other transistors are not. Finally, at t.sub.9, register 10 switches back to the active mode when CLK again transitions, and the next data bit, shown as D2 in FIG. 2, is then processed in the same manner described above with respect to D1.
While register 10 and its operation has been long used and established in the art, recall that at the outset of this Background section it was noted that speed through devices is a key consideration. Further, note now that a register may indeed be a key component in many of the critical paths of a system where speed is desirable. Indeed, in the context of registers there is often an analysis of various attributes such as set up time and hold time, where these two attributes combine to form the throughput time of the device. Given these attributes, it is most often the goal to reduce the throughput time of the device, that is, to improve the speed of operation of the register. Accordingly, the present inventor endeavors in the preferred embodiments to reduce the data throughput time of a register such as register 10 or other storage circuits detailed later, while further attempting to minimize or avoid any tradeoff that may present itself from the speed improvement.
By way of further background to speed enhancements, it is noted that some techniques exist in general circuit design to increase device speed. For example, the sizes of transistors may be increased to produce a corresponding increase in device speed. As another example, one performance technique currently in use in manufacturing is to target the threshold voltage of transistors given certain circuit expectations. Particularly, typically a manufacturer will build transistors, or make available transistor fabrication processes, which include transistors of a given threshold voltage. When providing this process, the manufacturer typically considers the tradeoff in speed improvement versus power consumption. To increase operational speed, it is known that the threshold voltage of all of the transistors within a circuit may be reduced. By reducing the threshold voltage, the drive current of these transistors is increased and, hence, the throughput time is improved.
While the above approaches are representative of the art for advancing circuit operational speed, they provide various limitations or drawbacks. For example, increasing transistor sizes creates higher cost in area and power. As another example, by reducing the threshold voltage of all transistors in a circuit, the leakage current of the circuit is also increased. Moreover, the ability to lower all transistor threshold voltages becomes even more limiting as power supply voltages are reduced and the threshold voltage of the transistor becomes a greater percentage of the power supply voltage. Still further, leakage current becomes a greater concern when there are inactive or standby periods, particularly where those periods may be relatively long. Thus, often a manufacturer anticipates a certain level of leakage to be the acceptable limit, and in view of that limit, adjusts known parameters so that each of the transistors of the circuit share a designated threshold voltage which will not exceed that limit.
The inventor of the present embodiments has recognized the above considerations and below are set forth embodiments which provide increased circuit speed while reducing leakage current as compared to the current state of the art.